Describe what info we're snarfing out of the prebuilt kernel.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

It's not safe to assume that the data section is 8-byte aligned.
Assuming 4-byte alignment seems to work however, and results in
simpler code than arbitrary alignment support.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>

Build an EFI image as a post build step.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Add argument parsing and use os.path.join where possible to support
building on windows.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

There is following error when compiling applications using smp:

  /zephyr/include/mgmt/smp.h:77:16: error: field 'zst_work' has \
  incomplete type
     77 |  struct k_work zst_work;
        |                ^~~~~~~~
  /zephyr/include/mgmt/smp.h:80:16: error: field 'zst_fifo' has \
  incomplete type
     80 |  struct k_fifo zst_fifo;
        |                ^~~~~~~~

Fix that by adding missing kernel.h include statement in mgmt/smp.h.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>

The hardware stack overflow feature requires
CONFIG_THREAD_STACK_INFO enabled in order to distingush
stack overflows from other causes when we get an exception.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

--warnings-as-errors was basically doing nothing, it is the default.
Replace this with an option to disable erroring on warning:

 -W, --disable-warnings-as-errors

Fixes #26910
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Conditional API was removed by preprocessor which violates zephyr
coding style. Removed ifdefs around conditional API.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>

Add devicetree overlay for connecting an Mikroe ETH click shield to an
NXP LPCXpresso55S69 development board.

The LPCXpresso55S69 uses SSEL1 (CS1) for mikroBUS SPI, whereas the
generic Mikroe ETH click board definition assumes SPI CS0.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>

Replaces .conf type configuration with .defconfig.
Makes configuration conditional, it depends on shield definition and
networking.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>

Includes support for spi, usb, i2c, uart, pwm, adc, dfu,
and onboard led and switch.
Signed-off-by: Brian Bradley <brian.bradley.p@gmail.com>

Transfers are cancelled on suspend event, OUT transfers
needs to be re-trigger on resume.
Rework event handling to filter out spurious resume
events and re-trigger transfer if previous event was
a suspend event.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>

Log which endpoint transfer will be cancelled.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>

The parameters for this fuel gauge depend on the hardware design and
the expected battery.  These should not be defaulted to a value that
may be inappropriate.  Require that they be explicitly provided.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>

Add a note in 2.4 release notes regarding SW_VECTOR_RELAY
feature, now supported also in Mainline Cortex-M architecture.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>

When BT_LL_SPLIT is not selected, it should not be visible.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>

These configs are not generic.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>

These configs are not generic
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>

The dependency to LL_SPLIT is removed.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>

These configs are not generic.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>

By splitting it out to a separate file, it will become easier to
separate generic and non-generic controller features.
This commit only contains the simple extraction.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>

The current shield version shows different configuration, including
disabling default ethernet and wifi interfaces.  To allow easy
connection from standard headers, this add two new shield designations.
The existing boards overlays and defconfig were updated.

The documentation was update to reflect changes. A new supported
variations section helps to understand what shield variation user need
select to build their own system.

This changes requires changes on esp32 offload tests to reflect new
esp_8266 shield designations. Sam4e_xpro was keeped as the only one
with dedicated overlay and both frdm_k64f and disco_l475_iot1 were
moved to use standard arduino r3 header using extra args.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>

The esp_8266 shield was added without owner on #24710. Add myself as
an owner of esp_8266 shield files.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>

Clean up the code some, and disable CONFIG_TIMESLICE_SIZE=1
until #13813 is resolved.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Exercise the public macros as well as device_map().
This test has a whitelist for whatever reason; add
mps2_an385 so that the !DEVICE_MMIO_IS_IN_RAM stuff
is tested.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Add some overview documentation on how to use this header.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This isn't needed any more, all of these directives were
for drivers which use device_map() now.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This gets a little complicated as the driver could be
using PCI-E MMIO, MMIO specified by DTS, or I/O ports.
This driver doesn't use struct uart_device_config any
more.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Replaces custom runtime calls to map memory.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Good example of the NAMED variants of the MMIO macros, since
an existing inheritance mechanism already took the first-member
slot of the dev_data/config structs.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Fairly straightforward example of how to deal with PCIe.
The code considers whether a particular instance is PCIe
or not on a per-instance basis, so DEVICE_MMIO_ROM is not
conditionally defined.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Straightforward example on how to use the TOPLEVEL variants
of the DEVICE_MMIO macros.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

A hack was required for the loapic code due to the address
range not being in DTS. A bug was filed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

The ethernet driver no longer continues to try to initialize
itself if PCIe probing fails.

This device is always PCIe so we don't need to reserve ROM MMIO
storage.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This driver code uses PCIe and doesn't use Zephyr's
device model, so we can't use the nice DEVICE_MMIO macros.
Set stuff up manually instead using device_map().
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Three variants provided:

- Drivers with one MMIO region to manage
- Drivers with multiple MMIO regions to manage
- Drivers or driver-like code which doesn't use Zephyr's device
  model
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This currently only supports identity paging; there's just
enough here for device_map() calls to work.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This will be the interface for mapping memory in the kernel's
part of the address space, which is guaranteed to be persistent
regardless of what thread is scheduled.

Further code for specifically managing virtual memory will end up in
kernel/mmu.c.

Further defintions for memory management in general will end up
in sys/mem_manage.h.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This is the low-level arch function to map a region into page
tables.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

This config indicates that a memory management unit is present
and enabled, which will in turn allow arch APIs to allow
mapping memory to be used.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>