RiscVar

Project information

Goal of this project is the creation of a RISC-V processor with a partially custom instruction set, that can be adjusted at runtime through the integration of an eFPGA. The eFPGA is created using the FABulous Framework, an open source framework to create eFPGAs.

RISC-V FPGA eFPGA

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README
CERN Open Hardware Licence Version 2 - Weakly Reciprocal

Created on

April 16, 2025

Copy SSH clone URLgit@gitlab.cs.hs-rm.de:yreis001/riscvar.git
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