Skip to content

E
eFPGA

Projects with this topic

Sort by:
  • View RiscVar project

    yreis001 / RiscVar

    Goal of this project is the creation of a RISC-V processor with a partially custom instruction set, that can be adjusted at runtime through the integration of an eFPGA. The eFPGA is created using the FABulous Framework, an open source framework to create eFPGAs.

    RISC-V FPGA eFPGA
    1
    Updated
    1 0 8
    Updated