Explore projects

Goal of this project is the creation of a RISC-V processor with a partially custom instruction set, that can be adjusted at runtime through the integration of an eFPGA. The eFPGA is created using the FABulous Framework, an open source framework to create eFPGAs.

HS_RM HWP

Aufgaben für das Fach Mikroprozessortechnik

FreeRTOS HAL Architecture Layer

FreeRTOS HAL Buildsystem

FreeRTOS HAL Driver