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FreeRTOS HAL Maschine Layer

FreeRTOS HAL Maschine Layer

FreeRTOS HAL Maschine Layer

FreeRTOS HAL Maschine Layer

Goal of this project is the creation of a RISC-V processor with a partially custom instruction set, that can be adjusted at runtime through the integration of an eFPGA. The eFPGA is created using the FABulous Framework, an open source framework to create eFPGAs.

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.