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Goal of this project is the creation of a RISC-V processor with a partially custom instruction set, that can be adjusted at runtime through the integration of an eFPGA. The eFPGA is created using the FABulous Framework, an open source framework to create eFPGAs.

Programmcode für Bachelorarbeit "Konzeption und prototypische Umsetzung einer Integration einer Internet-of-Things-Plattform mit einer Datenanalyse-Plattform". Dazu gehören die Anwnedungsfälle und die Flink- und Kafka-Server.

simple python implementation of SHA-1 and SHA-3 [only PoC]

The mkimage tool for RPi. This repo is just for convenience, as the official repo also contains 3 huge toolchains.

Application-Independent System on Chip

The mkimage tool for RPi. This repo is just for convenience, as the official repo also contains 3 huge toolchains.

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

OMG DDS implementation in Rust with a model driven approach to tailor the application.

Zweiter Prototyp eines autonomen Modellfahrzeugs, verwendet BeagleBoard-X15

fork of Binsec repository on Gitlab