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Frontend und Backend von Subato

IntelliJ-Plugin für Subato

Dokumentation von Subato

Dokumentation und Tools zum Subato Task Exchange Format (STEF)

Goal of this project is the creation of a RISC-V processor with a partially custom instruction set, that can be adjusted at runtime through the integration of an eFPGA. The eFPGA is created using the FABulous Framework, an open source framework to create eFPGAs.

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